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   -> Volume 3, Issue 15


Paper: Disributed Memory and Control VLSI Architectures ....
 
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elias@athina.cdsp.neu.edu (Prof. Elias S. Manolakos)
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PostPosted: Mon Dec 02, 2002 1:23 pm    
Subject: Paper: Disributed Memory and Control VLSI Architectures ....
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Paper: Disributed Memory and Control VLSI Architectures ....

The Postcript version of the following paper (vsp94.ps) is available thru
the world wide web (www). Use mosaic to open URL http://www.cdsp.neu.edu/.
Then look under "CDSP Research Groups" for the preprints of publications
of the Parallel Processing and Architectures research group.

If you do not have access to www use ftp to site ftp.cdsp.neu.edu.
Login as guest and look under /pub/papers/manolakos for the file vsp94.ps.
If you have any comments/questions feel free to contact the authors.

TITLE: Disributed Memory and Control VLSI Architectures for the
1-D Discrete Wavelet Transform

AUTHORS: Jose' Fridman, jfridman@cdsp.neu.edu
Elias S. Manolakos, elias@cdsp.neu.edu

to appear in the Proc. of VLSI Signal Processing VII,
La Jolla, October 1994.

ABSTRACT

In this paper, we address the synthesis of fast, efficient and regular
computational structures for the Discrete Wavelet Transform (DWT)
algorithm, using linear space-time mapping and constraint driven localization
techniques. Index space transformations are used to regularize the DWT
algorithm and to avoid data collisions due to multiprojection.
A summary of the data dependence and localization analysis is presented,
as well as an array of $L$ Processing Elements (PEs) for computing any
$J$-octave DWT decomposition with latency (parallel run time) of $M$,
where $L$ is the wavelet filter length and $M$ is the input sequence length.
The latency is independent of the highest computable octave $J$, for any
value of $J$, and the efficiency is nearly perfect (100\%) and independent
of $M$. The proposed parallel architecture is the fastest distributed
memory implementation of the 1-D DWT with $L$ PEs that we know of.
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