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   -> Volume 3, Issue 11


Preprint: On the synthesis of regular VLSI architectures...
 
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elias@athina.cdsp.neu.edu (Prof. Elias S. Manolakos)
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PostPosted: Mon Dec 02, 2002 1:12 pm    
Subject: Preprint: On the synthesis of regular VLSI architectures...
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Preprint: On the synthesis of regular VLSI architectures...

The Postcript version of the paper is available thru the world wide
web. Use mosaic to open URL http://www.cdsp.neu.edu/. Then look
under "CDSP Research Groups" for the preprints of publications of the
Parallel Processing and Architectures research group.
The ftp site is ftp.cdsp.neu.edu. Login as guest and look
under /pub/papers/manolakos.
If you have any comments/questions feel free to contact the authors.

TITLE: On the synthesis of regular VLSI architectures for the 1-D Discrete
Wavelet Transform

AUTHORS: Jose' Fridman, jfridman@cdsp.neu.edu
Elias S. Manolakos, elias@cdsp.neu.edu

to appear in the Proc. of the SPIE Conf. on Mathematical Imaging:
Wavelet Applications in Signal and Image Processing,
San Diego, July 1994.

ABSTRACT

A systematic methodology for deriving parallel computational
structures has been applied to the Discrete Wavelet Transform algorithm.
It is based on constraint driven localization, index space transformations
and linear space-time mapping.
The data dependence analysis shows that the DWT algorithm is characterized
by a regular structure along parallel scale planes with irregularities
between them, and that it is neither a Regular Iterative nor a Locally
Recursive Algorithm. The Dependence Graph (DG) of the DWT algorithm may
be described as an exponential pyramid consisting of ``stacked" planes of
convolution with decimation. The exponential tapering of the DG severely
restricts the feasibility of linear space-time mappings in general.
However, it is still possible to map the algorithm to a regular array with
local communication links by performing first a nonlinear transformation
on the index space that regularizes the inter-octave dependencies.
Then the computations of the equivalent algorithm may be executed
without collisions on a regular 1-D systolic array under a
simple to implement linear schedule. The synthesized array can compute
efficiently up to J=3 octaves, employing only L processing elements (L is the
number of wavelet filter coefficients). It achieves latency (parallel
running time) of 3M/2, where M is the size of the input sequence, using only
O(J) local memory per PE and distributed control (no global routing network
is necessary). Furthermore we prove that, in the general case, linear
scheduling causes severe inefficiencies when applied to the 1-D DWT algorithm
with more than $J=4$ octaves. Future work includes the synthesis of
efficient regular VLSI architectures with O(L) PEs for computing DWT's with
arbitrary J.
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